@phdthesis {Simula.simula.506,
	title = {Cost Effective Routing Implementations for On-Chip Networks},
	year = {2010},
	school = {Universidad Polit{\'e}cnica de Valencia},
	type = {phd},
	abstract = {Current many-core architectures like Chip Multiprocessors (CMPs) and Multiprocessor System-on-Chips (MPSoCs) rely on the effectiveness of the on-chip network (NoC) for inter-core communication. An effective NoC has to be scalable while meeting tight power, area, and latency constraints. 2D mesh topologies are usually preferred for general-purpose NoC designs as they fit the chip layout. However, designers must address new emerging challenges. The increased probability of manufacturing defects, the need for an optimized use of resources to enhance application-level parallelism or the need for efficient power-aware techniques may break the regularity in those topologies. In addition, collective communication support is a desired feature to effectively address communication needs from cache coherence protocols. Under these conditions, efficient routing of messages becomes a challenge. The objective of this dissertation is to lay the foundations of a new logic-based distributed routing architecture that is able to adapt to any irregular topology derived from a 2D mesh structure, thus providing full coverage for any topology pattern induced by any of the challenges mentioned above. And this take is done, first by starting from the grounds of a concept idea, then looking through an evolution of several mechanisms and finally, arriving to a final implementation that encompasses several modules accomplishing the objective mentioned before. In fact, this last implementation is named eLBDR (effective Logic-Based Distributed Routing), but the study will span from the first mechanism, LBDR, to the next mechanisms that have been emerged progressively, describing them in detail accompanied with evaluations and results to show a cost/applicability trade-off analysis. Referring to the full architecture, eLBDR presents area, latency and power consumption requirements that are comparable to the most efficient solutions in routing mechanisms like Dimension-Order-Routing (DOR), reflected on real router implementations designed with first attempts of bringing ideas that are still underutilised in the NoC domain, like virtual cut-through switching. NoC scenarios modelled after link variability analysis show a 100\% coverage achievement of the full mechanism in all scenarios that were configured. So, it is fair to assume that eLBDR is prepared to face the new challenges present in the NoC research field. eLBDR can be used as an effective fault-tolerant mechanism in CMP and MPSoC systems with defective components at the NoC level, aggressive power-down techniques switching off entire irregularly shaped NoC regions can be designed as the remaining network topology is still supported by eLBDR, virtualization of the chip (mapping applications to disjoint paths) can be also achieved with eLBDR by defining disjoint network regions, and finally, eLBDR allows the use of broadcast communication primitives to support effective cache coherency protocols. Broadcast is allowed inside a region in eLBDR and previous alternatives, thus implementing multicast support at the chip level. In short, the objective of the concept idea is to offer an alternative to the use of routing tables (either at routers or at end-nodes). Although the use of routing tables at routers is extremely flexible, it does not scale in terms of latency, area, and power consumption. As described in the next chapters, all mechanisms require a small set of configuration bits, thus being more compact than large routing tables implemented in memories. More important, from the first mechanism to the most recent developed, the requirements of any of them, do not grow with system size, thus providing scalability.},
	author = {Samuel Rodrigo {Mocholi}}
}
