@article {TROTTER2020189,
	title = {Cache simulation for irregular memory traffic on multi-core CPUs: Case study on performance models for sparse matrix{\textendash}vector multiplication},
	journal = {Journal of Parallel and Distributed Computing},
	volume = {144},
	year = {2020},
	month = {06/2020},
	pages = {189--205},
	publisher = {Elsevier},
	abstract = {Parallel computations with irregular memory access patterns are often limited by the memory subsystems of multi-core CPUs, though it can be difficult to pinpoint and quantify performance bottlenecks precisely. We present a method for estimating volumes of data traffic caused by irregular, parallel computations on multi-core CPUs with memory hierarchies containing both private and shared caches. Further, we describe a performance model based on these estimates that applies to bandwidth-limited computations. As a case study, we consider two standard algorithms for sparse matrix{\textendash}vector multiplication, a widely used, irregular kernel. Using three different multi-core CPU systems and a set of matrices that induce a range of irregular memory access patterns, we demonstrate that our cache simulation combined with the proposed performance model accurately quantifies performance bottlenecks that would not be detected using standard best- or worst-case estimates of the data traffic volume.},
	keywords = {AMD Epyc, Cache simulation, Intel Xeon, Performance model, Sparse matrix{\textendash}vector multiplication},
	issn = {0743-7315},
	doi = {https://doi.org/10.1016/j.jpdc.2020.05.020},
	url = {http://www.sciencedirect.com/science/article/pii/S0743731520302999},
	author = {James D. {Trotter} and Langguth, Johannes and Cai, Xing}
}
