@article {Simula.simula.2620,
	title = {Efficient and Cost-Effective Hybrid Congestion Control for HPC Interconnection Networks},
	journal = {IEEE Transactions on Parallel and Distributed Systems},
	volume = {26},
	number = {pp},
	year = {2015},
	pages = {107-119},
	publisher = {IEEE},
	abstract = {Interconnection networks are key components in High-Performance Computing (HPC) systems, their performance having a strong influence on the overall system one. However, at high load, congestion and its negative effects (e.g. Head-of-line blocking) threaten the performance of the network, and so the one of the entire system. Congestion control (CC) is crucial to ensure an efficient utilization of the interconnection network during congestion situations. As one major trend is to reduce the effective wiring in interconnection networks to reduce cost and power consumption, the network will operate very close to its capacity. Thus, congestion control becomes essential. Existing CC techniques can be divided into two general approaches. One is to throttle traffic injection at the sources that contribute to congestion, and the other is to isolate the congested traffic in specially designated resources. However, both approaches have different, but non-overlapping weaknesses: injection throttling techniques have a slow reaction against congestion, while isolating traffic in special resources may lead the system to run out of those resources. In this paper we propose EcoCC, a new Efficient and Cost-Effective CC technique, that combines injection throttling and congested-flow isolation to minimize their respective drawbacks and maximize overall system performance. This new strategy is suitable for current commercial switch architectures, where it could be implemented without requiring significant complexity. Experimental results, using simulations under synthetic and real tracebased traffic patterns, show that this technique improves by up to 55\% over some of the most successful congestion control techniques.},
	doi = {10.1109/TPDS.2014.2307851},
	author = {Escudero-Sahuquillo, Jes{\'u}s and Ernst Gunnar {Gran} and Pedro J. {Garcia} and Flich, Jos{\'e} and Skeie, Tor and Lysne, Olav and Francisco Jos{\'e} {Quiles} and Duato, Jose}
}
@article {Simula.simula.2218,
	title = {A New Proposal to Deal With Congestion in InfiniBand-Based Fat-Trees},
	journal = {Journal of Parallel and Distributed Computing},
	volume = {74},
	number = {1},
	year = {2014},
	month = {January},
	pages = {1802-1819},
	publisher = {Elsevier},
	abstract = {The overall performance of High-Performance Computing applications may depend largely on the performance achieved by the network interconnecting the end-nodes, thus high-speed interconnect technologies like InfiniBand are used to provide high throughput and low latency. Nevertheless, network performance may be degraded due to congestion, thus using techniques to deal with the problems derived from congestion has become practically mandatory. In this paper we propose a straightforward congestion-management method suitable for fat-tree topologies built from InfiniBand components. Our proposal is based on a traffic-flow-to-service-level mapping that prevents, as much as possible with the resources available in current InfiniBand components (basically Virtual Lanes), the negative impact of the two most common problems derived from congestion: head-of-line blocking and buffer-hogging. We also provide a mathematical approach to analyze the efficiency of our proposal and several ones, by means of a set of analytical metrics. In certain traffic scenarios, we observe up to a 68\% of the ideal performance gain that could be achieved in HoL-blocking and buffer-hogging prevention.},
	keywords = {Congestion management, Fat-trees, High-performance computing, InfiniBand, Interconnection networks},
	doi = {http://dx.doi.org/10.1016/j.jpdc.2013.09},
	author = {Escudero-Sahuquillo, Jes{\'u}s and Pedro Javier {Garc{\'\i}a} and Francisco Jos{\'e} {Quiles} and Reinemo, Sven-Arne and Skeie, Tor and Lysne, Olav and Duato, Jose}
}
@article {Simula.ND.41,
	title = {A Survey and Evaluation of Topology Agnostic Routing Algorithms},
	journal = {IEEE Transactions on Parallel and Distributed Systems},
	volume = {23},
	number = {3},
	year = {2012},
	month = {March},
	pages = {405-425},
	publisher = {IEEE},
	abstract = {Most standard interconnect technologies that have emerged over the last decade, mainly for clusters, are flexible with respect to network topology. This has spawned a substantial amount of research on topology agnostic routing algorithms, and some of the developed algorithms are widely deployed. These algorithms make no assumption about the structure of the network, thus they provide the flexibility needed to route on a network in the presence of faulty components. On the other hand, the advent of massive multi-core chips challenges the state of the art in interconnection networks. The topology of choice for point to point Networks on-chip (NoC) is the two dimensional mesh which is well understood, but the need of high yield, out of a production line for such chips requires that they should be functional even if some components suffer from manufacturing defects. Such defects will turn the regular topology into a slightly irregular one, making topology dependent routing algorithms inapplicable. Also, heterogeneous multi-core chips, where different cores could have different sizes and shapes, naturally lead to (slightly) irregular topologies. Therefore, topology agnostic routing algorithms proposed for clusters find a new environment to be applied since they provide the flexibility needed to route on a NoC in the presence of faulty or missing components. Moreover, in some cases, they have been shown to perform comparably to special purpose algorithms for regular topologies. Unfortunately, the existing topology agnostic routing algorithms have been developed for varying purposes, giving them different and not always comparable properties. Furthermore, the information on these routing algorithms is scattered on different papers where they have been evaluated under different and not comparable conditions. In this paper, we present a comprehensive overview of the topology agnostic routing algorithms that have been proposed to date. The algorithms are classified with respect to their most important properties, and their performance under equal, but varying conditions is analyzed. Thereby, we provide significant new insight into the properties of the different routing algorithms, and give substantial support for, given a set of requirements, finding the most suitable both for the on and off-chip environments.},
	author = {Flich, Jos{\'e} and Skeie, Tor and Mej{\'\i}a, Andres and Lysne, Olav and Lopez, Pedro and Robles, Antonio and Duato, Jose and Koibuchi, Michihiro and Rokicki, Tomas and Sancho, Jos{\'e}}
}
@inproceedings {Simula.simula.834,
	title = {Combining Congested-Flow Isolation and Injection Throttling in HPC Interconnection Networks},
	journal = {International Conference on Parallel Processing, ICPP 2011},
	year = {2011},
	month = {September},
	pages = {662-672},
	publisher = {IEEE Computer Society},
	type = {Conference},
	abstract = {Existing congestion control mechanisms in interconnects can be divided into two general approaches. One is to throttle traffic injection at the sources that contribute to congestion, and the other is to isolate the congested traffic in specially designated resources. These two approaches have different, but non-overlapping weaknesses. In this paper we present in detail a method that combines injection throttling and congested-flow isolation. Through simulation studies we first demonstrate the respective flaws of the injection throttling and of flow isolation. Thereafter we show that our combined method extracts the best of both approaches in the sense that it gives fast reaction to congestion, it is scalable and it has good fairness properties with respect to the congested flows.},
	isbn = {978-1-4577-1336-1},
	doi = {10.1109/ICPP.2011.80},
	author = {Escudero-Sahuquillo, Jes{\'u}s and Ernst Gunnar {Gran} and Pedro Javier {Garc{\'\i}a} and Flich, Jos{\'e} and Skeie, Tor and Lysne, Olav and Francisco Jos{\'e} {Quiles} and Duato, Jose},
	editor = {Bilof, Randall}
}
@article {Simula.simula.512,
	title = {Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems},
	journal = {IEEE Transactions on Computed Aided Design},
	volume = {30},
	number = {4},
	year = {2011},
	month = {April},
	pages = {534-547},
	publisher = {IEEE},
	abstract = {The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of using routing tables. uLBDR requires a small set of configuration bits, thus being more practical than large routing tables implemented in memories. Several implementations of uLBDR are presented highlighting the tradeoff between routing cost and coverage. The alternatives span from the previously proposed LBDR approach (with 30\% of coverage) to the uLBDR mechanism achieving full coverage. This comes with a small performance cost, thus exhibiting the tradeoff between fault tolerance and performance. Power consumption, area, and delay estimates are also provided highlighting the efficiency of the mechanism. To do this, different router models (one for CMPs and one for MPSoCs) have been designed as a proof concept.},
	doi = {10.1109/TCAD.2011.2119150},
	author = {Samuel Rodrigo {Mocholi} and Flich, Jos{\'e} and Roca, Antoni and Medardoni, Simone and Bertozzi, Davide and Camacho, Jesus and Silla, Federico and Duato, Jose}
}
@article {Simula.ND.64,
	title = {Dynamic Fault Tolerance in Fat-Trees},
	journal = {IEEE Transactions on Computers},
	volume = {60},
	number = {4},
	year = {2011},
	month = {April},
	pages = {508-525},
	publisher = {IEEE},
	abstract = {Fat-trees are a very common communication architecture in current large-scale parallel computers. The probability of failure increases with the number of components. We present a routing method for deterministically and adaptively routed fat trees, applicable to both distributed and source routing, that is able to handle several concurrent faults and that transparently returns to the original routing strategy once the faulty components have recovered. The method is local and dynamic, completely masking the fault from the rest of the system. It only requires a small extra functionality in the switches to handle misrouting around a fault. The method guarantees connectedness and deadlock and livelock freedom for up to radix/2 -1 arbitrary simultaneous faults. Our simulation experiments show a graceful degradation of performance as faults are added. Furthermore, they demonstrate that for most fault combinations, our method will even be able to handle significantly more faults beyond the radix/2-1 limit with high probability.},
	doi = {10.1109/TC.2010.97},
	author = {Frank Olaf {Sem-Jacobsen} and Skeie, Tor and Lysne, Olav and Duato, Jose}
}
@inproceedings {Simula.simula.510,
	title = {Addressing Manufacturing Challenges With Cost-Efficient Fault Tolerant Routing},
	journal = {NOCS {\textquoteright}10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip},
	year = {2010},
	pages = {25-32},
	publisher = {IEEE Computer Society},
	type = {Conference},
	isbn = {ISBN: 978-0-7695-4053-5},
	doi = {10.1109/NOCS.2010.12},
	author = {Samuel Rodrigo {Mocholi} and Flich, Jos{\'e} and Roca, Antoni and Medardoni, Simone and Bertozzi, Davide and Camacho, Jesus and Silla, Federico and Duato, Jose},
	editor = {IEEE Computer {Society}}
}
@article {Simula.simula.422,
	title = {Buffer Management Strategies to Reduce HoL Blocking},
	journal = {IEEE Transactions on Parallel and Distributed Systems},
	volume = {21},
	number = {6},
	year = {2009},
	pages = {739-753},
	publisher = {IEEE},
	author = {Nachiondo, T. and Flich, J. and Duato, Jose}
}
@techreport {Simula.nd.413,
	title = {Dynamic Fault Tolerance in Fat-Trees - Research Note},
	year = {2009},
	month = {November},
	publisher = {Simula},
	abstract = {Fat-trees are a very common communication architecture in current large-scale parallel computers. The probability of failure in these systems increases with the number of components. We present a routing method for deterministically and adaptively routed fat-trees, applicable to both distributed and source routing, that is able to handle several concurrent faults and that transparently returns to the original routing strategy once the faulty components have recovered. The method is local and dynamic, completely masking the fault from the rest of the system. It only requires a small extra functionality in the switches to handle misrouting around a fault. The method guarantees connectedness and deadlock and livelock freedom for up to k -1 arbitrary simultaneous switch and/or link faults where k is half the number of ports in the switches. Our simulation experiments show a graceful degradation of performance as more faults occur. Furthermore, we demonstrate that for most fault combinations, our method will even be able to handle significantly more faults beyond the k-1 limit with high probability.},
	author = {Frank Olaf {Sem-Jacobsen} and Skeie, Tor and Lysne, Olav and Duato, Jose}
}
@article {Simula.simula.518,
	title = {Efficient Implementation of Distributed Routing Algorithms for NoCs},
	journal = {IET Computers \& Digital Techniques},
	volume = {3},
	number = {5},
	year = {2009},
	month = {September},
	pages = {460-475},
	doi = {10.1049/iet-cdt.2008.0092},
	author = {Samuel Rodrigo {Mocholi} and Medardoni, Simone and Flich, Jos{\'e} and Bertozzi, Davide and Duato, Jose}
}
@article {Simula.simula.410,
	title = {Region-Based Routing: a Mechanism to Support Efficient Routing Algorithms in NoCs},
	journal = {IEEE Transactions on Very Large Scale Integration},
	volume = {17},
	number = {3},
	year = {2009},
	pages = {356-369},
	publisher = {IEEE},
	author = {Mejia, A. and Palesi, M. and Flich, J. and Kumar, S. and Lopez, Pedro and Holsmark, R. and Duato, Jose}
}
@inproceedings {Simula.simula.516,
	title = {Yield-Oriented Evaluation Methodology of Network-on-Chip Routing Implementations},
	journal = {SOC{\textquoteright}09 Proceedings of the 11th international conference on System-on-chip},
	year = {2009},
	publisher = {IEEE},
	type = {Conference},
	isbn = {978-1-4244-4466-3},
	doi = {10.1109/SOCC.2009.5335667},
	author = {Samuel Rodrigo {Mocholi} and Hernandez, Carles and Flich, Jos{\'e} and Silla, Federico and Duato, Jose and Medardoni, Simone and Bertozzi, Davide and Mej{\'\i}a, Andres and Dai, Donglai},
	editor = {IEEE, }
}
@article {Simula.ND.22,
	title = {An Efficient and Deadlock-Free Network Reconfiguration Protocol},
	journal = {IEEE Transactions on Computers},
	volume = {57},
	number = {6},
	year = {2008},
	month = {June},
	pages = {762-779},
	abstract = {Component failures and planned component replacements cause changes in the topology and routing paths supplied by the interconnection network of a parallel processor system over time. Such changes may require the network to be reconfigured such that the existing routing function is replaced by one which enables packets to reach their intended destinations amid the changes. Efficient reconfiguration methods are desired that allow the network to function uninterruptedly over the course of the reconfiguration process while remaining free from deadlocking behavior. In this paper, we propose, evaluate, and prove deadlock freedom of a new network reconfiguration protocol that overlaps various phases of {\textquotedblleft}static{\textquotedblright} reconfiguration processes traditionally used in commercial and research systems to provide performance efficiency on par with that of recently proposed {\textquotedblleft}dynamic{\textquotedblright} reconfiguration processes, but without their complexity. Simulation results show that the proposed Overlapping Static Reconfiguration protocol can reduce reconfiguration time by up to 50\%, reduce packet latency by several orders of magnitude, reduce packet dropping by an order of magnitude, and provide unhalted packet injection as compared to traditional static reconfiguration while allowing network throughput similar to dynamic reconfiguration.},
	author = {Lysne, Olav and Jose Miguel {Montanana} and Flich, Jos{\'e} and Duato, Jose and Timothy Mark {Pinkston} and Skeie, Tor}
}
@article {Simula.simula.418,
	title = {Efficient Deadline-Based QoS Algorithms for High-Performance Networks},
	journal = {IEEE Transactions on Computers},
	volume = {57},
	number = {7},
	year = {2008},
	pages = {928-939},
	publisher = {IEEE},
	doi = {10.1109/TC.2008.39},
	author = {Vicente, A.M and Apostolopoulos, G. and Alfaro, F.J and S{\'a}nchez, J.L and Duato, Jose}
}
@inproceedings {Simula.simula.522,
	title = {An Efficient Implementation of Distributed Routing Algorithms for NoCs},
	journal = {Second ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2008},
	year = {2008},
	month = {April},
	pages = {87-96},
	publisher = {IEEE Computer Society},
	type = {Conference},
	abstract = {The design of NoCs for multi-core chips introduces new design constraints like power consumption, area, and ultra low latencies. Although 2D meshes are preferred, heterogeneous blocks, fabrication faults, reliability issues, and chip virtualization may lead to the need of irregular topologies or regions. In this situation, efficient routing becomes a challenge. Although the use of routing tables at switches is flexible, it does not scale in terms of latency and area due to its memory requirements. LBDR (logic-based distributed routing) is proposed as a new routing method that removes the need of using routing tables at all. LBDR enables the implementation of many routing algorithms on most of the practical topologies we might find in the near future in a multi-core system. From an initial topology and routing algorithm, a set of three bits per switch/output port is computed. Evaluation results show that, by using a small logic, LBDR mimics the performance of routing algorithms when implemented with routing tables, both in regular and irregular topologies.},
	isbn = {0-7695-3098-2},
	doi = {10.1109/NOCS.2008.4492728},
	author = {Flich, Jos{\'e} and Samuel Rodrigo {Mocholi} and Duato, Jose},
	editor = {IEEE Computer {Society}}
}
@inproceedings {Simula.simula.416,
	title = {Efficient Unicast and Multicast Support for CMPs},
	journal = {IEEE/ACM International Symposium on Microarchitecture},
	year = {2008},
	pages = {364-375},
	publisher = {IEEE Computer Society},
	type = {Conference},
	isbn = {978-1-4244-2836-6},
	author = {Samuel Rodrigo {Mocholi} and Flich, J. and Duato, Jose and Hummel, M.},
	editor = {Faraboschi, Paolo and Keckler, Steve}
}
@article {Simula.simula.430,
	title = {Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures},
	journal = {IEEE Transactions on Parallel and Distributed Systems},
	volume = {19},
	number = {8},
	year = {2008},
	pages = {1044-1056},
	publisher = {IEEE},
	author = {Fernandez-Pasqual, R. and Garcia, J.M and Acacio, M.A and Duato, Jose}
}
@inproceedings {Simula.ND.71,
	title = {On the Potential of NoC Virtualization for Multicore Chips},
	journal = {International Workshop on Multi-Core Computing Systems (MuCoCoS{\textquoteright}08)},
	year = {2008},
	month = {March},
	pages = {801-807},
	publisher = {IEEE},
	type = {Workshop},
	abstract = {As the end of Moores-law is on the horizon, power becomes a limiting factor to the continuous increases in performance gains for single-core processors. Processor engineers have shifted to the multicore paradigm and many-core processors are reality. Within the context of these multi-core, three key metrics point themselves out as being of major importance, performance, fault-tolerance (including yield), and power consumption. A solution that optimizes all three of these metric is challenging. As the number of cores increases the importance of the interconnection network-on-chip (NoC) grows as well, and chip designers should aim to optimize these three key metrics. In this paper we identify and discuss the main properties that a NoC must exhibit in order to enable such optimizations. In particular, we propose the use of virtualization techniques at the NoC level. The implementation of routing algorithms for NoC is a key design parameter in order to achieve an effective virtualization of the chip that should also support broadcast within the virtualized context. The intention behind this paper is for it to serve a position paper on the topic of virtualization for NoC and the challenges that should be met at the routing layer in order to maximize performance, fault-tolerance and power consumption.},
	author = {Flich, Jos{\'e} and Samuel Rodrigo {Mocholi} and Duato, Jose and S{\o}dring, Thomas and {\r A}shild Gr{\o}nstad {Solheim} and Skeie, Tor and Lysne, Olav},
	editor = {Pllana, Sabri}
}
@article {Simula.ND.277,
	title = {On the Potential of NoC Virtualization for Multicore Chips},
	journal = {Scalable Computing: Practice and Experience},
	volume = {9},
	number = {3},
	year = {2008},
	month = {September},
	pages = {165-177},
	abstract = {As the end of Moores-law is on the horizon, power becomes a limiting factor to continuous increases in performance gains for single-core processors. Processor engineers have shifted to the multicore paradigm and many-core processors are a reality. Within the context of these multicore chips, three key metrics point themselves out as being of major importance, performance, fault-tolerance (including yield), and power consumption. A solution that optimizes all three of these metrics is challenging. As the number of cores increases the importance of the interconnection network-on-chip (NoC) grows as well, and chip designers should aim to optimize these three key metrics in the NoC context as well. In this paper we identify and discuss the main properties that a NoC must exhibit in order to enable such optimizations. In particular, we propose the use of virtualization techniques at the NoC level. As a major finding, we identify the implementation of unicast and broadcast routing algorithms to become a key design parameter in order to achieve an effective virtualization of the chip. The intention behind this paper is for it to serve as a position paper on the topic of virtualization for NoC and the challenges that should be met at the routing layer in order to optimize performance, fault-tolerance and power consumption in multicore chips.},
	author = {Flich, Jos{\'e} and Samuel Rodrigo {Mocholi} and Duato, Jose and S{\o}dring, Thomas and {\r A}shild Gr{\o}nstad {Solheim} and Skeie, Tor and Lysne, Olav}
}
@article {Simula.ND.70,
	title = {A Proposal for Managing ASI Fabrics},
	journal = {Journal of Systems Architecture},
	volume = {54},
	number = {7},
	year = {2008},
	month = {July},
	pages = {664-678},
	abstract = {Recent years, computer performance has been significantly increased. As a con-sequence, data I/O systems have become bottlenecks within systems. To alleviate this problem, Advanced Switching was recently proposed as a new standard for future interconnects. The Advanced Switching specification establishes a fabric man-agement infrastructure, which is in charge of updating the set of fabric paths each time a topological change takes place. The use of source routing and passive switches makes unfeasible the adaptation to this new technology of many existing proposals to handle topological changes in switched interconnection networks. This paper presents a fabric management mechanism for Advanced Switching, but also suitable for other source routing interconnects. Furthermore, the work presents a detailed performance evaluation for this proposal. This evaluation allows us to identify the main drawbacks of the mechanism and to define future improvements.},
	author = {Antonio Robles {G{\'o}mez} and Berm{\'u}dez, Aurelio and Casado, Rafael and Francisco Jos{\'e} {Quiles} and Skeie, Tor and Duato, Jose}
}
@inproceedings {Reinemo.2007.1,
	title = {Boosting Ethernet Performance by Segment-Based Routing},
	journal = {Proceedings of the 15th Euromicro Conference on Parallel, Distributed and Network-based Processing (PDP 2007)},
	year = {2007},
	month = {February},
	pages = {55-62},
	publisher = {IEEE Computer Society Press},
	type = {Conference},
	abstract = {In this paper we embed an efficient topology agnostic routing algorithm with fault tolerance capabilities into back-pressured Ethernet technology. This makes it possible to use off-the-shelf equipment to build cost-effective systems with an efficient use of all network components. This stands in contrast to the inefficient use of network resources (links) supported by the Spanning Tree Protocol (STP). The Segment-Based Routing Algorithm (SR) is a deterministic routing algorithm that achieves high performance without the use of virtual channels. Furthermore, it is topology agnostic, meaning it can handle any topology and any combination of faults derived from the original topology when combined with static reconfiguration. Through simulations we verify an overall improvement in throughput by a factor of 1.2 to 10.0 compared to the conventional Ethernet routing algorithm, the STP, and other topology agnostic routing algorithms such as Up*/Down* and Tree-based Turn-prohibition, which both are applicable to Ethernet.},
	isbn = {0-7695-2784-1},
	author = {Reinemo, Sven-Arne and Skeie, Tor and Mej{\'\i}a, Andres and Flich, Jos{\'e} and Duato, Jose},
	editor = {D{\textquoteright}Ambra, Pasqua and Mario Rosario {Guarracino}}
}
@inproceedings {Simula.simula.420,
	title = {Deterministic Versus Adaptive Routing in Fat-Trees},
	journal = {IEEE International Parallel and Distributed Processing Symposium},
	year = {2007},
	pages = {292-300},
	publisher = {IEEE Computer Society},
	type = {1},
	isbn = {1-4244-0909-8},
	author = {Gomez, C. and Gilabert, F. and M. E. {G{\'o}mez} and Lopez, Pedro and Duato, Jose},
	editor = {Dhabaleswar K. {Panda}}
}
@article {Simula.simula.412,
	title = {Handling Topology Changes in InfiniBand},
	journal = {IEEE Transactions on Parallel and Distributed Systems},
	volume = {8},
	number = {12},
	year = {2007},
	pages = {172-185},
	publisher = {IEEE},
	author = {Bermudez, A. and Casado, R. and Francisco Jos{\'e} {Quiles} and Duato, Jose}
}
@article {Simula.simula.3064,
	title = {A Latency-Aware Partitioning Method for Distributed Virtual Environment Systems},
	journal = {IEEE Transactions on Parallel and Distributed Systems},
	volume = {18},
	number = {9},
	year = {2007},
	pages = {1215-1226},
	publisher = {IEEE},
	author = {Morillo, P. and Rueda, S. and J. M. {Orduna} and Duato, Jose}
}
@article {Simula.simula.424,
	title = {A New Cost-Effective Technique for QoS Support in Clusters},
	journal = {IEEE Transactions on Parallel and Distributed Systems},
	volume = {18},
	number = {12},
	year = {2007},
	pages = {1714-1726},
	publisher = {IEEE},
	author = {Martinez, A. and Alfaro, F.J and S{\'a}nchez, J.L and Francisco Jos{\'e} {Quiles} and Duato, Jose}
}
@inproceedings {Sem-jacobsen.2006.1,
	title = {Dynamic Fault Tolerance With Misrouting in Fat Trees},
	journal = {Proceedings of the International Conference on Parallel Processing (ICPP)},
	year = {2006},
	month = {August},
	pages = {33-45},
	publisher = {IEEE Computer Society},
	type = {Conference},
	abstract = {Fault tolerance is critical for efficient utilisation of large computer systems. Dynamic fault tolerance allows the network to remain available through the occurance of faults as opposed to static fault tolerance which requires the network to be halted to reconfigure it. Although dynamic fault tolerance may lead to less efficient solutions than static fault tolerance, it allows for a much higher availability of the system. In this paper we devise a dynamic fault tolerant adaptive routing algorithm for the fat tree, a much used interconnect topology, which relies on misrouting around link faults. We show that we are guaranteed to tolerate any combination of less than (num\_switch\_ports/2) link faults without the need for additional network resources for deadlock freedom. There is also a high probability of tolerating an even larger number of link faults. Simulation results show that network performance degrades very little when faults are dynamically tolerated.},
	isbn = {22},
	author = {Frank Olaf {Sem-Jacobsen} and Skeie, Tor and Lysne, Olav and Duato, Jose},
	editor = {Feng, Wu-chi}
}
@article {Simula.simula.414,
	title = {Fast Routing Computation on InfiniBand Networks},
	journal = {IEEE Transactions on Parallel and Distributed Systems},
	volume = {17},
	number = {3},
	year = {2006},
	pages = {215-226},
	publisher = {IEEE},
	author = {Bermudez, A. and Casado, R. and Francisco Jos{\'e} {Quiles} and Duato, Jose}
}
@misc {Simula.simula.494,
	title = {Fremgangsm{\r a}te Og Innretning for Nettverkskonfigurering},
	year = {2006},
	author = {Lysne, Olav and Duato, Jose and Pinkston, T.}
}
@article {Gomez.2006.1,
	title = {A Routing Methodology for Achieving Fault Tolerance in Direct Networks},
	journal = {IEEE Transactions on Computers},
	volume = {55},
	number = {4},
	year = {2006},
	month = {April},
	pages = {400-415},
	abstract = {Massively parallel computing systems are being built with thousands of nodes. The interconnection network plays a key role for the performance of such systems. However, the high number of components significantly increases the probability of failure. Additionally, failures in the interconnection network may isolate a large fraction of the machine. It is therefore critical to provide an efficient fault-tolerant mechanism to keep the system running, even in the presence of faults. This paper presents a new fault-tolerant routing methodology that does not degrade performance in the absence of faults and tolerates a reasonably large number of faults without disabling any healthy node. In order to avoid faults, for some source-destination pairs, packets are first sent to an intermediate node and then from this node to the destination node. Fully adaptive routing is used along both subpaths. The methodology assumes a static fault model and the use of a checkpoint/restart mechanism. However, there are scenarios where the faults cannot be avoided solely by using an intermediate node. Thus, we also provide some extensions to the methodology. Specifically, we propose disabling adaptive routing and/or using misrouting on a per-packet basis. We also propose the use of more than one intermediate node for some paths. The proposed fault-tolerant routing methodology is extensively evaluated in terms of fault tolerance, complexity, and performance.},
	author = {Maria Engracia {G{\'o}mez} and Nils Agne {Nordbotten} and Flich, Jos{\'e} and Lopez, Pedro and Robles, Antonio and Duato, Jose and Skeie, Tor and Lysne, Olav}
}
@inproceedings {Mejia.2006.1,
	title = {Segment-Based Routing: an Efficient Fault-Tolerant Routing Algorithm for Meshes and Tori},
	journal = {20th IEEE International Parallel \& Distributed Processing Symposium},
	year = {2006},
	month = {April},
	pages = {1-10},
	publisher = {IEEE Computer Society},
	type = {Conference},
	address = {Washington, USA},
	abstract = {Computers get faster every year, but the demand for computing resources seems to grow at an even faster rate. Science keeps demanding more processing power for calculations and simulations, growth in E-commerce requires powerful servers to offer seamless online shopping, and massive multiplayer online games requires powerful and stable systems to keep their virtual worlds running 24 hours a day. Depending on the problem domain, this demand for more power can be satisfied by either, massively parallel computers, or clusters of computer. Common for both approaches is the dependence on high performance interconnect networks such as Myrinet, Infiniband, or 10 Gigabit Ethernet. While high throughput and low latency are key features of interconnection networks, the issue of fault-tolerance is now becoming increasingly important. As the number of network components grows so does the probability for failure, thus it becomes important to also consider the fault-tolerance mechanism of interconnection networks. The main challenge then lies in combining performance and fault-tolerance, while still keeping cost and complexity low. This paper proposes a new deterministic routing methodology for tori and meshes, which achieves high performance without the use of virtual channels. Furthermore, it is topology agnostic in nature, meaning it can handle any topology derived from any combination of faults when combined with static reconfiguration. The algorithm, referred to as Segment-based Routing (SR), works by partitioning a topology into subnets, and subnets into segments. This allows us to place bidirectional turn restrictions locally within a segment. As segments are independent, we gain the freedom to place turn restrictions within a segment independently from other segments. This results in a larger degree of freedom when placing turn restrictions compared to other routing strategies. In this paper a way to compute segment-based routing tables is presented and applied to meshes and tori. Preliminary evaluation results show that the concept of segments leads to an increase in performance by a factor of 1.8 over FX and up*/down* routing.},
	isbn = {1-4244-0054-6},
	author = {Mej{\'\i}a, Andres and Flich, Jos{\'e} and Duato, Jose and Reinemo, Sven-Arne and Skeie, Tor},
	editor = {Ali, Shaukat}
}
@inproceedings {Mora.2006.1,
	title = {Towards and Efficient Switch Architecture for High-Radix Switches},
	journal = {ACM/IEEE Symposium on Architectures for Networking and Communications Systems},
	year = {2006},
	month = {December},
	pages = {11-20},
	publisher = {ACM Press},
	type = {Conference},
	isbn = {1-59593-580-0},
	author = {Mora, Gaspar and Flich, Jos{\'e} and Duato, Jose and Lopez, Pedro and Lysne, Olav},
	editor = {Dubois, Michel and Eatherton, Will}
}
@article {Lysne.2005.2,
	title = {A Methodology for Developing Deadlock-Free Dynamic Network Reconfiguration Processes},
	journal = {IEEE Transactions on Parallel and Distributed Systems},
	volume = {16},
	number = {5},
	year = {2005},
	month = {May},
	pages = {428-443},
	publisher = {IEEE},
	abstract = {Dynamic network reconfiguration is defined as the process of changing from one routing function to another while the network remains up and running. The main challenge is in avoiding deadlock anomalies while keeping restrictions on packet injection and forwarding minimal. Current approaches either require virtual channels in the network or they work only for a limited set of routing algorithms and/or fault patterns. In this paper, we present a methodology for devising deadlock free and dynamic transitions between old and new routing functions that is consistent with recently proposed theory. The methodology is independent of topology, can be applied to any deadlock-free routing function, and puts no restrictions on the routing function changes that can be supported. Furthermore, it does not require any virtual channels to guarantee deadlock freedom. This research is motivated by current trends toward using increasingly larger Internet and transaction processing servers based on clusters of PCs that have very high availability and dependability requirements, as well as other local, system, and storage area network-based computing systems.},
	isbn = {1045-9219},
	doi = {10.1109/TPDS.2005.59},
	author = {Lysne, Olav and Timothy Mark {Pinkston} and Duato, Jose}
}
@article {Duato.2005.1,
	title = {A Theory for Deadlock-Free Dynamic Network Reconfiguration},
	journal = {IEEE Transactions on Parallel and Distributed Systems},
	volume = {16},
	number = {5},
	year = {2005},
	month = {May},
	pages = {412-427},
	abstract = {This paper develops theoretical support useful for determining deadlock properties of dynamic network reconfiguration techniques and serves as a basis for the development of design methodologies useful for deriving such techniques. It is applicable to interconnection networks typically used in multiprocessor servers, network-based computing clusters and distributed storage systems, and also has potential application to system-on-chip networks. This theory builds on basic principles established by previous theories while pioneering new concepts fundamental to the case of dynamic reconfiguration.},
	author = {Duato, Jose and Lysne, Olav and Pang, Ruoming and Timothy Mark {Pinkston}}
}
@inproceedings {Lysne.2004.1,
	title = {Simple Deadlock-Free Dynamic Network Reconfiguration},
	journal = {High Performance Computing - HiPC 2004: 11th International Conference, Bangalore, India, December 19-22, 2004},
	year = {2004},
	month = {December},
	pages = {504-515},
	publisher = {Springer Verlag},
	type = {1},
	author = {Lysne, Olav and Jose Miguel {Montanana} and Timothy Mark {Pinkston} and Duato, Jose and Skeie, Tor and Flich, Jos{\'e}},
	editor = {Victor Prasanna L {Bouge}}
}
