@phdthesis {Simula.simula.1514,
	title = {Topology Agnostic Methods for Routing, Reconfiguration and Virtualization of Interconnection Networks},
	year = {2012},
	school = {University of Oslo},
	type = {phd},
	abstract = {Modern computing systems, such as supercomputers, data centers and multicore chips, generally require efficient communication between their different system units; tolerance towards component faults; flexibility to expand or merge; and a high utilization of their resources. Interconnection networks are used in a variety of such computing systems in order to enable communication between their diverse system units. Investigation and proposal of new or improved solutions to topology agnostic routing and reconfiguration of interconnection networks are main objectives of this thesis. In addition, topology agnostic routing and reconfiguration algorithms are utilized in the development of new and flexible approaches to processor allocation. The thesis aims to present versatile solutions that can be used for the interconnection networks of a number of different computing systems. No particular routing algorithm was specified for an interconnection network technology which is now incorporated in Dolphin Express. The thesis states a set of criteria for a suitable routing algorithm, evaluates a number of existing routing algorithms, and recommend that one of the algorithms - which fulfils all of the criteria - is used. Further investigations demonstrate how this routing algorithm inherently supports fault-tolerance, and how it can be optimized for some network topologies. These considerations are also relevant for the InfiniBand interconnection network technology. Reconfiguration of interconnection networks (change of routing function) is a deadlock prone process. Some existing reconfiguration strategies include deadlock avoidance mechanisms that significantly reduce the network service offered to running applications. The thesis expands the area of application for one of the most versatile and efficient reconfiguration algorithms available in the literature, and proposes an optimization of this algorithm that improves the network service offered to running applications. Moreover, a new reconfiguration algorithm is presented that supports a replacement of the routing function without causing performance penalties. Processor allocation strategies that guarantee traffic-containment commonly pose strict requirements on the shape of partitions, and thus achieve only a limited utilization of a system\&$\#$39;s computing resources. The thesis introduces two new approaches that are more flexible. Both approaches utilize the properties of a topology agnostic routing algorithm in order to enforce traffic-containment within arbitrarily shaped partitions. Consequently, a high resource utilization as well as isolation of traffic between different partitions is achieved.},
	author = {{\r A}shild Gr{\o}nstad {Solheim}}
}
@inproceedings {Simula.ND.303,
	title = {Efficient and Contention-Free Virtualisation of Fat-Trees},
	journal = {IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum},
	year = {2011},
	month = {September},
	pages = {754-760},
	publisher = {IEEE Computer Society Washington},
	type = {Workshop},
	address = {Washington DC, USA},
	abstract = {Maintaining high system utilisation is a key factor for data centres. However, strictly partitioning the datacentre resources to fully isolate the concurrent applications (contention freedom) leads to poor system utilisation because of fragmentation. We present an allocation algorithm for fat-trees (which are commonly found in large-scale data centres) capable of increasing system utilisation while maintaining application isolation. Results show at least a 10\% increase in system utilization compared to regular contention free allocation mechanisms, at the cost of a slight reduction in network performance or application isolation.},
	isbn = {978-0-7695-4577-6},
	author = {Frank Olaf {Sem-Jacobsen} and {\r A}shild Gr{\o}nstad {Solheim} and Lysne, Olav and Skeie, Tor and S{\o}dring, Thomas}
}
@article {Simula.ND.101,
	title = {A Dynamic Distributed Mechanism for Reconfiguring High-Performance Networks},
	journal = {Parallel Computing},
	volume = {35},
	number = {5},
	year = {2009},
	pages = {305-312},
	publisher = {Elsevier},
	doi = {10.1016/j.parco.2008.12.011},
	author = {Robles-Gomez, Antonio and Berm{\'u}dez, Aurelio and Casado, Rafael and {\r A}shild Gr{\o}nstad {Solheim}}
}
@inproceedings {Simula.ND.54,
	title = {Efficient and Deadlock-Free Reconfiguration for Source Routed Networks},
	journal = {Communication Architecture for Clusters (CAC)},
	year = {2009},
	publisher = {IEEE Computer Society},
	type = {Workshop},
	abstract = {Overlapping Reconfiguration is currently the most efficient method to reconfigure an interconnection network, but is only valid for systems that apply distributed routing. This paper proposes a solution which enables utilization of Overlapping Reconfiguration in a source routed environment. We demonstrate how a synchronized injection of tokens has a significant impact on the performance of the method. Furthermore, we propose and evaluate an optimization of the original algorithm that reduces (and in some cases even eliminates) performance issues caused by the token forwarding regime, such as increased latency and decreased throughput.},
	isbn = {978-1-4244-3750-4},
	author = {{\r A}shild Gr{\o}nstad {Solheim} and Lysne, Olav and Berm{\'u}dez, Aurelio and Casado, Rafael and S{\o}dring, Thomas and Skeie, Tor and Robles-Gomez, Antonio},
	editor = {Yang, Yuanyuan}
}
@inproceedings {Simula.ND.293,
	title = {A Framework for Routing and Resource Allocation in Network Virtualization},
	journal = {International Conference on High Performance Computing (HiPC{\textquoteright}09)},
	year = {2009},
	pages = {129-139},
	publisher = {IEEE},
	type = {Conference},
	abstract = {Computer architectures for high performance computing have traditionally been based on an assumption of one parallel application running alone on one machine. The current trend is, however, that huge computer installations offer compute power to a set of users or customers, each demanding only a subset of the available compute resources. This places new requirements on the architecture, in that it must support dynamic partitioning of the resources into several virtual servers as demand changes. We introduce a novel framework which supports flexible formation of such virtual servers while preventing interference between the communication of different virtual servers. This paper investigates the impacts of a shared interconnection network on applications running on virtual compute servers. We show that the interconnect performance supplied to each job is highly unpredictable, and that a job can experience a performance degradation of 97\% when its traffic interferes with the traffic of concurrent jobs. With a minor reduction in the utilization of each processing node, this can be considerably improved through a combination of routing-containment in the interconnection network and a carefully designed resource allocation strategy.},
	isbn = {978-1-4244-4921-7},
	author = {{\r A}shild Gr{\o}nstad {Solheim} and Lysne, Olav and Skeie, Tor and S{\o}dring, Thomas and Reinemo, Sven-Arne},
	editor = {Yang, Yuanyuan and Parashar, M. and Muralidhar, R. and V. K. {Prasanna}}
}
@inbook {Simula.ND.279,
	title = {Network Reconfiguration in High-Performance Interconnection Networks},
	booktitle = {Autonomic Computing and Networking},
	year = {2009},
	pages = {313-332},
	publisher = {Springer},
	organization = {Springer},
	chapter = {8},
	abstract = {High-performance interconnection networks like InfiniBand, ASI, Autonet andMyrinet have the property of link level flow control. As such alterating the routing function while the network is operational is a complex process, because the danger of packet deadlocks must be addressed. Over the last 5-6 years this problem has been addressed and solved by the research community. This chapter collects several proposals for updating a routing function in interconnection networks after the occurrence of a topological change. Both traditional and recent reconfiguration schemes are covered, and the selection includes both technology-dependant and generic techniques.},
	isbn = {978-0-387-89827-8},
	author = {Casado, Rafael and Berm{\'u}dez, Aurelio and Robles-Gomez, Antonio and Lysne, Olav and Skeie, Tor and {\r A}shild Gr{\o}nstad {Solheim} and S{\o}dring, Thomas},
	editor = {Mieso K. {Denko} and Laurence Tianruo {Yang} and Zhang, Yan}
}
@article {Simula.ND.87,
	title = {A New Distributed Management Mechanism for ASI Based Networks},
	journal = {Computer Communications},
	volume = {32},
	number = {2},
	year = {2009},
	pages = {294-304},
	publisher = {Elsevier},
	doi = {10.1016/j.comcom.2008.10.010},
	author = {Robles-Gomez, Antonio and Berm{\'u}dez, Aurelio and Casado, Rafael and {\r A}shild Gr{\o}nstad {Solheim} and S{\o}dring, Thomas and Skeie, Tor}
}
@inproceedings {Simula.ND.295,
	title = {RecTOR: a New and Efficient Method for Dynamic Network Reconfiguration},
	journal = {Euro-Par 2009},
	year = {2009},
	pages = {1052-1064},
	publisher = {Springer Berlin / Heidelberg},
	type = {Conference},
	abstract = {Reconfiguration of an interconnection network is fundamental for the provision of a reliable service. Current reconfiguration methods either include deadlock-avoidance mechanisms that impose performance penalties during the reconfiguration, or are tied to the Up*/Down* routing algorithm which achieves relatively low performance. In addition, some of the methods require complex network switches, and some are limited to distributed routing systems. This paper presents a new dynamic reconfiguration method, RecTOR, which ensures deadlock-freedom during the reconfiguration without causing performance degradation such as increased latency or decreased throughput. Moreover, it is based on a simple concept, is easy to implement, is applicable for both source and distributed routing systems, and assumes Transition-Oriented Routing which achieves excellent performance. Our simulation results confirm that RecTOR supports a better network service to the applications than Overlapping Reconfiguration does.},
	isbn = {978-3-642-03868-6},
	author = {{\r A}shild Gr{\o}nstad {Solheim} and Lysne, Olav and Skeie, Tor},
	editor = {Epema H. {Sips} and Lin, H.-X.}
}
@inproceedings {Simula.ND.103,
	title = {An Analysis of Connectivity and Yield for 2D Mesh Based NoC With Interconnect Router Failures},
	journal = {11th EUROMICRO Conference on Digital System Design (DSD)},
	year = {2008},
	month = {September},
	publisher = {University of Parma},
	type = {Conference},
	abstract = {The manufacturing process of modern day processors is both costly and complex and there are many different factors that influence the quality of a chip when it comes off the production line. Typically, hundreds of chips are manufactured from a single silicon wafer and as we go deeper into the sub-micron era of microchip manufacturing, the potential for defects during production increases. The advent of multi-core computing may introduce problems related to connectivity and yield for high volume manufacturing (HVM). In this paper we explore potential benefits that fault tolerant routing provides within the NoC (network-on-chip) paradigm with a study of the relationship between connectivity and yield at the interconnect routing level. For dimension-order routing based mesh NoCs, we describe two methods that are logically straightforward to implement and that can be used to increase the yield of chips with interconnect router faults.},
	isbn = {978-0-7695-3277-6},
	author = {S{\o}dring, Thomas and {\r A}shild Gr{\o}nstad {Solheim} and Skeie, Tor and Reinemo, Sven-Arne},
	editor = {Fanucci, Luca}
}
@inproceedings {Simula.ND.88,
	title = {Deadlock-Free Dynamic Network Reconfiguration Based on Close Up*/Down* Graphs},
	journal = {Euro-Par 2008},
	year = {2008},
	pages = {940-949},
	publisher = {Springer Berlin / Heidelberg},
	type = {Conference},
	isbn = {978-3-540-85450-0},
	author = {Robles-Gomez, Antonio and Berm{\'u}dez, Aurelio and Casado, Rafael and {\r A}shild Gr{\o}nstad {Solheim}},
	editor = {Luque, E. and Margalef, T. and Ben{\textquoteleft}{\"\i}tez, D.}
}
@techreport {Simula.ND.100,
	title = {Deadlock-Free Dynamic Network Reconfiguration Based on Close Up*/Down* Graphs},
	year = {2008},
	publisher = {University of Castilla-La Mancha},
	author = {Robles-Gomez, Antonio and Berm{\'u}dez, Aurelio and Casado, Rafael and {\r A}shild Gr{\o}nstad {Solheim}}
}
@article {Simula.ND.18,
	title = {The Interconnection Network - Architectural Challenges for Utility Computing Data Centres},
	journal = {IEEE Computer Magazine},
	volume = {41},
	number = {9},
	year = {2008},
	month = {September},
	pages = {62-69},
	publisher = {IEEE},
	abstract = {The mode of operation employed by Computational Data Centres that offer Utility Computing differs significantly from that of traditional supercomputers and server clusters and as such present new architectural problems that should be studied and solved. In this paper we concentrate on issues facing the interconnection network. We argue that this is a part of the overall architecture where shortcomings in present day solutions are most severe and present a model for the mode of operation of a Utility Computing Data Centre where virtualisation is a main ingredient. Based on this model we identify several areas where the interconnection network faces new challenges and needs new solutions. In each of these areas we give a brief introduction to previous results before we identify the new challenges.},
	author = {Lysne, Olav and Reinemo, Sven-Arne and Skeie, Tor and {\r A}shild Gr{\o}nstad {Solheim} and S{\o}dring, Thomas and Lars Paul {Huse} and Bj{\o}rn Dag {Johnsen}}
}
@inproceedings {Simula.ND.71,
	title = {On the Potential of NoC Virtualization for Multicore Chips},
	journal = {International Workshop on Multi-Core Computing Systems (MuCoCoS{\textquoteright}08)},
	year = {2008},
	month = {March},
	pages = {801-807},
	publisher = {IEEE},
	type = {Workshop},
	abstract = {As the end of Moores-law is on the horizon, power becomes a limiting factor to the continuous increases in performance gains for single-core processors. Processor engineers have shifted to the multicore paradigm and many-core processors are reality. Within the context of these multi-core, three key metrics point themselves out as being of major importance, performance, fault-tolerance (including yield), and power consumption. A solution that optimizes all three of these metric is challenging. As the number of cores increases the importance of the interconnection network-on-chip (NoC) grows as well, and chip designers should aim to optimize these three key metrics. In this paper we identify and discuss the main properties that a NoC must exhibit in order to enable such optimizations. In particular, we propose the use of virtualization techniques at the NoC level. The implementation of routing algorithms for NoC is a key design parameter in order to achieve an effective virtualization of the chip that should also support broadcast within the virtualized context. The intention behind this paper is for it to serve a position paper on the topic of virtualization for NoC and the challenges that should be met at the routing layer in order to maximize performance, fault-tolerance and power consumption.},
	author = {Flich, Jos{\'e} and Samuel Rodrigo {Mocholi} and Duato, Jose and S{\o}dring, Thomas and {\r A}shild Gr{\o}nstad {Solheim} and Skeie, Tor and Lysne, Olav},
	editor = {Pllana, Sabri}
}
@article {Simula.ND.277,
	title = {On the Potential of NoC Virtualization for Multicore Chips},
	journal = {Scalable Computing: Practice and Experience},
	volume = {9},
	number = {3},
	year = {2008},
	month = {September},
	pages = {165-177},
	abstract = {As the end of Moores-law is on the horizon, power becomes a limiting factor to continuous increases in performance gains for single-core processors. Processor engineers have shifted to the multicore paradigm and many-core processors are a reality. Within the context of these multicore chips, three key metrics point themselves out as being of major importance, performance, fault-tolerance (including yield), and power consumption. A solution that optimizes all three of these metrics is challenging. As the number of cores increases the importance of the interconnection network-on-chip (NoC) grows as well, and chip designers should aim to optimize these three key metrics in the NoC context as well. In this paper we identify and discuss the main properties that a NoC must exhibit in order to enable such optimizations. In particular, we propose the use of virtualization techniques at the NoC level. As a major finding, we identify the implementation of unicast and broadcast routing algorithms to become a key design parameter in order to achieve an effective virtualization of the chip. The intention behind this paper is for it to serve as a position paper on the topic of virtualization for NoC and the challenges that should be met at the routing layer in order to optimize performance, fault-tolerance and power consumption in multicore chips.},
	author = {Flich, Jos{\'e} and Samuel Rodrigo {Mocholi} and Duato, Jose and S{\o}dring, Thomas and {\r A}shild Gr{\o}nstad {Solheim} and Skeie, Tor and Lysne, Olav}
}
@techreport {25342,
	title = {The Interconnection Network - Architectural Challenges for Utility Computing Data Centres},
	year = {2007},
	note = {This technical report is an earlier version of a published journal article. The published version can be found here:https://www.simula.no/publications/interconnection-network-architectural-challenges-utility-computing-data-centres},
	publisher = {Simula Research Laboratory},
	author = {Lysne, Olav and Reinemo, Sven-Arne and Skeie, Tor and {\r A}shild Gr{\o}nstad {Solheim} and S{\o}dring, Thomas and Lars Paul {Huse} and Bj{\o}rn Dag {Johnsen}}
}
@inproceedings {Simula.ND.25,
	title = {Routing-Contained Virtualization Based on Up*/Down* Forwarding},
	journal = {High Performance Computing - HiPC 2007},
	year = {2007},
	pages = {500-513},
	publisher = {Springer-Verlag},
	type = {Conference},
	edition = {4873},
	address = {Berlin Heidelberg},
	abstract = {Virtualization of computing resources is becoming increasingly important both in high-end servers and in multi-core CPUs. In a virtualized system, the set of resources that constitute a virtual compute entity should be spatially separated from each other. Dividing the cores on a chip, or the CPUs in a high end server into disjoint sets for each task is a trivial problem. Ensuring that they use disjoint parts of the interconnection network is, however, complex, and in existing methods the requirement of routing-containment of each virtual partition severely degrades the utilization of the system. In this paper, we present an allocation strategy that is based on Up*/Down* routing. Through simulations, we demonstrate increases (in some cases above 30\%) in system utilization relative to state-of- the-art in a Dimension Order routed mesh - a topology that is assumed to be widely deployed in Networks on Chip.},
	isbn = {978-3-540-77219-4},
	author = {{\r A}shild Gr{\o}nstad {Solheim} and Lysne, Olav and S{\o}dring, Thomas and Skeie, Tor and Jakob Aleksander {Libak}},
	editor = {Aluru et {al.}}
}
@misc {Simula.ND.19,
	title = {The Realization of Virtual Compute Resources in a Utility Computing Data Center (UCDC) in the Many Core Era},
	howpublished = {2006 Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems},
	year = {2006},
	author = {Lysne, Olav and Reinemo, Sven-Arne and Skeie, Tor and {\r A}shild Gr{\o}nstad {Solheim} and S{\o}dring, Thomas}
}
@article {Solheim.2006.1,
	title = {Routing for the ASI Fabric Manager},
	journal = {IEEE Communications Magazine},
	volume = {44},
	number = {7},
	year = {2006},
	month = {July},
	pages = {39-44},
	author = {{\r A}shild Gr{\o}nstad {Solheim} and Lysne, Olav and Skeie, Tor and S{\o}dring, Thomas and Ingebj{\o}rg Thelin {Theiss} and Johnsen, Ian}
}
@misc {Theiss.2005.2,
	title = {SIVSS Deliverable 5.3, Simula Switch Feasibility and Research Contribution Report},
	howpublished = {Sixth framework programme, Commission of the European Communities, Proposal/Contract no.: 002075},
	year = {2005},
	author = {Ingebj{\o}rg Thelin {Theiss} and S{\o}dring, Thomas and {\r A}shild Gr{\o}nstad {Solheim}}
}
@misc {Sodring.2005.1,
	title = {SIVSS Deliverable 5.6, Simulation Model Showing MIN Architecture That Can Deliver Over 1 Tb/s Performance Using Single Stage 640 Gb/s Switches},
	howpublished = {Sixth framework programme, Commission of the European Communities, Proposal/Contract no.: 002075},
	year = {2005},
	author = {S{\o}dring, Thomas and {\r A}shild Gr{\o}nstad {Solheim} and Ingebj{\o}rg Thelin {Theiss}}
}
@misc {Theiss.2005.3,
	title = {SIVSS Deliverable 9.2, Research Report on Overall System Archicecture Resilience},
	howpublished = {Sixth framework programme, Commission of the European Communities, Proposal/Contract no.: 002075},
	year = {2005},
	author = {Ingebj{\o}rg Thelin {Theiss} and S{\o}dring, Thomas and {\r A}shild Gr{\o}nstad {Solheim} and Frank Olaf {Sem-Jacobsen}}
}
@misc {ND.8.Theiss.2004,
	title = {Deliverable 4.3, Simula Research Lab Switch Feasibility and Research Contribution Report},
	howpublished = {Project Scaleable Intelligent Video Server System (SIVSS), Sixth framework programme, Commission of the European Communities, Proposal/Contract no.: 002075},
	year = {2004},
	month = {December},
	author = {Theiss, I. and S{\o}dring, T. and {\r A}shild Gr{\o}nstad {Solheim} and Horn, G.}
}
