@misc {25118,
	title = {Heterogeneous Manycore Simulations in Cardiac Electrophysiology},
	howpublished = {Tenth International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2017), Stockholm, Sweden},
	year = {2017},
	abstract = {The demand for computing power in computational cardiology is continuously increasing due to the use of physiologically realistic cell models and the need to simulate the heart and use higher resolutions in time and space. And while parallel computing itself is widely used in the field by now, the arrival of heterogeneous multicore architectures presents an important opportunity for speeding up the cardiac simulation process. However, this speedup is not obtained effortlessly, and achieving it presents numerous computational challenges of its own.We present a summary of our experiences from the implementation of multiple cardiac research codes on multicore, manycore, and GPU processors. Our main goal is to highlight the platform-specific challenges we face in our applications, ranging from efficient data movement to optimizations for large-scale irregular computations. Based on that, we discuss the suitability of the different plattforms for cardiac computations.},
	author = {Langguth, Johannes and Cai, Xing and Chai, Jun}
}
@article {19137,
	title = {Communication-Hiding Programming for Clusters with Multi-Coprocessor Nodes},
	journal = {Concurrency and Computation: Practice and Experience},
	volume = {27},
	year = {2015},
	note = {Published online before print.},
	month = {05/2015},
	pages = {4172{\textendash}4185},
	publisher = {John Wiley \& Sons, Ltd},
	abstract = {Future exascale systems are expected to adopt compute nodes that incorporate many accelerators. To shed some light on the upcoming software challenge, this paper investigates the particular topic of programming clusters that have multiple Xeon Phi coprocessors in each compute node. A new offload approach is considered for intra-node communication, which combines Intel\&rsquo;s APIs of coprocessor offload infrastructure (COI) and symmetric communication interface (SCIF) for achieving low latency. While the conventional pragma-based offload approach allows simpler programming, the COI-SCIF approach has three advantages in (1) lower overhead associated with launching offloaded code, (2) higher data transfer bandwidths, and (3) more advanced asynchrony between computation and data movement. The low-level COI-SCIF approach is also shown to have benefits over the MPI-OpenMP counterpart, which belongs to the symmetric usage mode. Moreover, a hybird programming strategy based on COI-SCIF is presented for joining the computational force of all CPUs and coprocessors, while realizing communication hiding. All the programming approaches are tested by a real-world 3D application, for which the COI-SCIF-based approach shows a performance advantage on Tianhe-2.},
	keywords = {hybrid programming, Intel Xeon Phi coprocessor, offload model, SCIF, Tianhe-2},
	doi = {10.1002/cpe.3507},
	author = {Dong, Xinnan and Wen, Mei and Chai, Jun and Cai, Xing and Zhao, Mandan and Zhang, Chunyuan}
}
@article {19103,
	title = {Parallel performance modeling of irregular applications in cell-centered finite volume methods over unstructured tetrahedral meshes},
	journal = {Journal of Parallel and Distributed Computing},
	volume = {76},
	year = {2015},
	month = {02/2015},
	pages = {120-131},
	publisher = {Elsevier},
	abstract = {Finite volume methods are widely used numerical strategies for solving partial differential equations. This paper aims at obtaining a quantitative understanding of the achievable performance of the cell-centered finite volume method on 3D unstructured tetrahedral meshes, using traditional multicore CPUs as well as modern GPUs. By using an optimized implementation and a synthetic connectivity matrix that exhibits a perfect structure of equal-sized blocks lying on the main diagonal, we can closely relate the achievable computing performance to the size of these diagonal blocks. Moreover, we have derived a theoretical model for identifying characteristic levels of the attainable performance as a function of hardware parameters, based on which a realistic upper limit of the performance can be predicted accurately. For real-world tetrahedral meshes, the key to high performance lies in a reordering of the tetrahedra, such that the resulting connectivity matrix resembles a block diagonal form where the optimal size of the blocks depends on the hardware. Numerical experiments confirm that the achieved performance is close to the practically attainable maximum and it reaches 75\% of the theoretical upper limit, independent of the actual tetrahedral mesh considered. From this, we develop a general model capable of identifying bottleneck performance of a system{\textquoteright}s memory hierarchy in irregular applications.},
	doi = {10.1016/j.jpdc.2014.10.005},
	author = {Langguth, Johannes and Wu, Nan and Chai, Jun and Cai, Xing}
}
@article {Simula.simula.2246,
	title = {Towards Simulation of Subcellular Calcium Dynamics at Nanometre Resolution},
	journal = {International Journal of High Performance Computing Applications},
	volume = {29},
	year = {2015},
	pages = {51-63},
	publisher = {SAGE},
	abstract = {Numerical simulation of subcellular\&nbsp;\&nbsp;dynamics with a resolution down to one nanometre can be an important tool for discovering the physiological cause of many heart diseases. The requirement of enormous computational power, however, has made such simulations prohibitive so far. By using up to 12,288 Intel Xeon Phi 31S1P coprocessors on the new hybrid cluster Tianhe-2, which is the new number one supercomputer of the world, we have achieved 1.27 Pflop/s in double precision, which brings us much closer to the nanometre resolution. This is the result of efficiently using the hardware on different levels: (1) a single Xeon Phi (2) a single compute node that consists of a host and three coprocessors, and (3) a huge number of interconnected nodes. To overcome the challenge of programming Intel{\textquoteright}s new many-integrated core (MIC) architecture, we have adopted techniques such as vectorization, hierarchical data blocking, register data reuse, offloading computations to the coprocessors, and pipelining computations with intra-/inter-node communications.},
	doi = {10.1177/1094342013514465},
	author = {Chai, Jun and Johan Elon {Hake} and Wu, Nan and Wen, Mei and Cai, Xing and Glenn T. {Lines} and Yang, Jing and Su, Huayou and Zhang, Chunyuan and Liao, Xiangke}
}
@inproceedings {Simula.simula.2872,
	title = {Utilizing Multiple Xeon Phi Coprocessors on One Compute Node},
	journal = {International Conference on Algorithms and Architectures for Parallel Processing},
	volume = {8631},
	year = {2014},
	pages = {68-81},
	publisher = {Springer},
	type = {Conference},
	address = {Berlin Heidelberg New York},
	doi = {10.1007/978-3-319-11194-0_6},
	author = {Dong, Xinnan and Chai, Jun and Yang, Jing and Wen, Mei and Wu, Nan and Cai, Xing and Zhang, Chunyuan and Chen, Zhaoyun},
	editor = {Sun, X.-H.}
}
@inproceedings {Simula.simula.2266,
	title = {On the GPU Performance of Cell-Centered Finite Volume Method Over Unstructured Tetrahedral Meshes},
	journal = {Proceedings of the 3rd Workshop on Irregular Applications: Architectures and Algorithms},
	year = {2013},
	publisher = {ACM},
	type = {Workshop},
	address = {New York},
	doi = {10.1145/2535753.2535765},
	author = {Langguth, Johannes and Wu, Nan and Chai, Jun and Cai, Xing},
	editor = {Tumeo, A. and Feo, J. and Villa, O. and Secchi, S.}
}
@article {Simula.simula.1394,
	title = {Resource-Efficient Utilization of CPU/GPU-Based Heterogeneous Supercomputers for Bayesian Phylogenetic Inference},
	journal = {The Journal of Supercomputing},
	volume = {66},
	number = {1},
	year = {2013},
	pages = {364-380},
	doi = {10.1007/s11227-013-0911-1},
	author = {Chai, Jun and Su, Huayou and Wen, Mei and Cai, Xing and Wu, Nan and Zhang, Chunyuan}
}
@article {Simula.simula.2098,
	title = {Simulating Cardiac Electrophysiology in the Era of GPU-Cluster Computing},
	journal = {IEICE Transactions on Information and Systems},
	volume = {E96-D},
	number = {12},
	year = {2013},
	pages = {2587-2595},
	doi = {10.1587/transinf.E96.D.2587},
	author = {Chai, Jun and Wen, Mei and Wu, Nan and Huang, Dafei and Yang, Jing and Cai, Xing and Zhang, Chunyuan and Yang, Qianming}
}
