@misc {27547,
	title = {System and method of computing ethernet routing paths},
	howpublished = {US Patent},
	number = {16/138,366},
	year = {2020},
	month = {12/2020},
	edition = {H04L45/02},
	chapter = {10855581},
	url = {https://patents.google.com/patent/US20190149461A1},
	author = {Camacho, Jesus and Skeie, Tor and Reinemo, Sven-Arne}
}
@misc {27083,
	title = {Method of computing balanced routing paths in fat-trees},
	howpublished = {Us Patent},
	number = {15/679, 974},
	year = {2019},
	month = {09/2019},
	edition = {H04L45/14},
	chapter = {US10425324B2},
	abstract = {A device and method for providing balanced routing paths in a computational grid including determining a type of topology of the computational grid having a plurality of levels, wherein each level includes a plurality of switches, determining whether the type of topology of the computational grid is a fat-tree, determining whether the fat-tree is odd, determining whether the fat-tree is a regular fat-tree, computing a first set of routing paths for the computational grid based on the determining of whether the fat-tree is odd and is a regular fat-tree, computing a second set of routing paths for the computational grid using a topology agnostic routing technique, and configuring forwarding tables in said switches with the first set of computed routing paths when the topology is determined to be a fat-tree and with the second set of computed routing paths when the topology is determined to not be a fat-tree.},
	url = {https://patents.google.com/patent/US10425324B2/en?oq=US10425324B2},
	author = {Camacho, Jesus and Skeie, Tor and Reinemo, Sven-Arne}
}
@misc {24627,
	title = {About Management of Exascale Systems},
	howpublished = {ExaComm 2016, Frankfurt},
	year = {2016},
	type = {Invited talk},
	author = {Skeie, Tor and Tasoulas, Evangelos and Zahid, Feroz and Ernst Gunnar {Gran} and Camacho, Jesus}
}
@article {24504,
	title = {Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems},
	journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
	volume = {30},
	year = {2011},
	pages = {534-547},
	publisher = {IEEE},
	author = {Rodrigo, Samuel and Flich, J. and Medardoni, S. and Bertozzi, D. and Camacho, Jesus and Silla, F. and Duato, J.}
}
@article {Simula.simula.512,
	title = {Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems},
	journal = {IEEE Transactions on Computed Aided Design},
	volume = {30},
	number = {4},
	year = {2011},
	month = {April},
	pages = {534-547},
	publisher = {IEEE},
	abstract = {The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of using routing tables. uLBDR requires a small set of configuration bits, thus being more practical than large routing tables implemented in memories. Several implementations of uLBDR are presented highlighting the tradeoff between routing cost and coverage. The alternatives span from the previously proposed LBDR approach (with 30\% of coverage) to the uLBDR mechanism achieving full coverage. This comes with a small performance cost, thus exhibiting the tradeoff between fault tolerance and performance. Power consumption, area, and delay estimates are also provided highlighting the efficiency of the mechanism. To do this, different router models (one for CMPs and one for MPSoCs) have been designed as a proof concept.},
	doi = {10.1109/TCAD.2011.2119150},
	author = {Samuel Rodrigo {Mocholi} and Flich, Jos{\'e} and Roca, Antoni and Medardoni, Simone and Bertozzi, Davide and Camacho, Jesus and Silla, Federico and Duato, Jose}
}
@inproceedings {Simula.simula.510,
	title = {Addressing Manufacturing Challenges With Cost-Efficient Fault Tolerant Routing},
	journal = {NOCS {\textquoteright}10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip},
	year = {2010},
	pages = {25-32},
	publisher = {IEEE Computer Society},
	type = {Conference},
	isbn = {ISBN: 978-0-7695-4053-5},
	doi = {10.1109/NOCS.2010.12},
	author = {Samuel Rodrigo {Mocholi} and Flich, Jos{\'e} and Roca, Antoni and Medardoni, Simone and Bertozzi, Davide and Camacho, Jesus and Silla, Federico and Duato, Jose},
	editor = {IEEE Computer {Society}}
}
