@inproceedings {42827,
	title = {Host Bypassing: Let your GPU speak Ethernet},
	journal = {IEEE 8th International Conference on Network Softwarization (NetSoft)},
	year = {2022},
	month = {06/2022},
	pages = {85-90},
	publisher = { IEEE},
	abstract = {Hardware acceleration of network functions is essential to meet the challenging Quality of Service requirements in nowadays computer networks. Graphical Processing Units (GPU) are a widely deployed technology that can also be used for computing tasks, including acceleration of network functions. In this work, we demonstrate how commodity GPUs, which do not provide any network interfaces, can be used to accelerate network functions. Our approach leverages PCIe peer-to-peer capabilities and allows the GPU to control the network interface card directly, without any assistance from the operating system or control application. The presented evaluation results demonstrate the feasibility of our approach and its performance of up to 10 Gbit/s, even for small packets.},
	isbn = {978-1-6654-0694-9},
	doi = {10.1109/NetSoft54395.2022.9844090},
	url = {https://ieeexplore.ieee.org/document/9844090},
	author = {Kundel, Ralf and Anderweit, Leonard and Markussen, Jonas and Griwodz, Carsten and Abboud, Osama and Becker, Benjamin and Meuser, Tobias},
	editor = {Clemm, Alexander and Clemm, Alexander}
}
@inproceedings {42826,
	title = {Host Bypassing: Direct Data Piping from the Network to the Hardware Accelerator},
	journal = {IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)},
	year = {2021},
	month = {12/2021},
	pages = {23-30},
	publisher = { IEEE},
	abstract = {Computer networks have become very important and influential over the last years for many common services such as Internet connectivity as well as time-sensitive applications such as videotelephony. Furthermore, approaches like in-network computing enable the offloading of latency-critical and high-performance network functions into the network, e.g. 5G network functions, to enable such time-sensitive applications. In this work, we show how FPGAs in PCIe-based systems, which are typically used as hardware accelerators for latency-critical in-network functions, can be integrated into the data path. Our approach, named host bypassing, allows direct data transfer from the network interface to the accelerator and accomplishes substantial performance benefits over existing state-of-the-art approaches. Our detailed evaluation results demonstrate the possibility of achieving deterministic low latency while operating under heavy load without any packet loss. In addition, fewer CPU resources are required.},
	isbn = {978-1-6654-3860-5},
	doi = {10.1109/MCSoC51149.2021.00012},
	url = {https://ieeexplore.ieee.org/document/9691977},
	author = {Kundel, Ralf and Eryigit, Kadir and Markussen, Jonas and Griwodz, Carsten and Abboud, Osama and Hark, Rhaban and Steinmetz, Ralf},
	editor = {Tee Hui {Teo} and Ben Abdallah, Abderazek}
}
