@article {Simula.simula.838,
	title = {An Efficient, Low-Cost Routing Framework for Convex Mesh Partitions to Support Virtualisation},
	journal = {ACM Transactions on Embedded Computing Systems},
	volume = {12},
	number = {4},
	year = {2013},
	month = {June},
	publisher = {ACM},
	abstract = {At the core of an efficient chip multiprocessors (CMP) is support for unicast and multicast routing, low implementation costs, and the ability to isolate concurrent applications with maximum utilization of the CMP. We present an efficient logic-based unicast and multicast routing algorithm that guarantees isolation of local application traffic within any near-convex region on the chip, and the algorithms to recognize supported partitions and configure the cores accordingly. Evaluations show that the routing algorithm has a 57 percent; more compact implementation than a recent multicast solution with the same coverage, and it achieves 5 percent; higher throughput with 13 percent; lower latency.},
	author = {Frank Olaf {Sem-Jacobsen} and Samuel Rodrigo {Mocholi} and Skeie, Tor and Strano, Alessandro and Bertozzi, Davide}
}
@article {Simula.simula.764,
	title = {Enabling Power Efficiency Through Dynamic Rerouting On-Chip},
	journal = {ACM Transactions on Embedded Computing Systems},
	volume = {12},
	number = {4},
	year = {2013},
	month = {June},
	publisher = {ACM},
	abstract = {Networks-on-chip (NoCs) are key components in many-core chip designs. Dynamic power-awareness is a new challenge present in NoCs that must be efficiently handled by the routing functionality as it introduces irregularities in the commonly used 2-D meshes. In this article, we propose a logic-based routing algorithm, iFDOR, oriented towards dynamic powering down one region within every application partition on the chip through dynamic rerouting, with low implementation costs. Results show that we can successfully shutdown an arbitrary rectangular region within an application partition without significant impact on network performance.},
	author = {Frank Olaf {Sem-Jacobsen} and Samuel Rodrigo {Mocholi} and Strano, Alessandro and Skeie, Tor and Bertozzi, Davide and Gilabert, Francisco}
}
@inproceedings {Simula.simula.1348,
	title = {Cost-Effective Contention Avoidance in a CMP With Shared Memory Controllers},
	journal = {Proceedings of Euro-Par 2012},
	year = {2012},
	month = {May},
	pages = {741-752},
	publisher = {Springer Berlin Heidelberg},
	type = {Conference},
	abstract = {Efficient CMP utilisation requires virtualisation. This forces multiple applications to contend for the same network resources and memory bandwidth. In this paper we study the cause and effect of network congestion with respect to traffic local to the applications, and traffic caused by memory access. This reveals that applications close to the memory controller suffer because of congestion caused by memory controller traffic from other applications. We present a simple mechanism to reduce head-of-line blocking in the switches, which efficiently reduces network congestion, increases network performance, and evens out the performance differences between the CMP applications.},
	keywords = {Conference},
	author = {Rodrigo, Samuel and Frank Olaf {Sem-Jacobsen} and Tatenguem, Herv{\'e} and Skeie, Tor and Bertozzi, Davide},
	editor = {Kaklamanis, Christos and Papatheodorou, Theodore and Paul G. {Spirakis}}
}
@techreport {Simula.simula.766,
	title = {Appendix to Enabling Power Efficiency Through Dynamic Rerouting On-Chip},
	year = {2011},
	month = {September},
	publisher = {Simula Research Laboratory},
	author = {Frank Olaf {Sem-Jacobsen} and Samuel Rodrigo {Mocholi} and Strano, Alessandro and Skeie, Tor and Bertozzi, Davide and Gilabert, Francisco}
}
@article {Simula.simula.512,
	title = {Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems},
	journal = {IEEE Transactions on Computed Aided Design},
	volume = {30},
	number = {4},
	year = {2011},
	month = {April},
	pages = {534-547},
	publisher = {IEEE},
	abstract = {The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of using routing tables. uLBDR requires a small set of configuration bits, thus being more practical than large routing tables implemented in memories. Several implementations of uLBDR are presented highlighting the tradeoff between routing cost and coverage. The alternatives span from the previously proposed LBDR approach (with 30\% of coverage) to the uLBDR mechanism achieving full coverage. This comes with a small performance cost, thus exhibiting the tradeoff between fault tolerance and performance. Power consumption, area, and delay estimates are also provided highlighting the efficiency of the mechanism. To do this, different router models (one for CMPs and one for MPSoCs) have been designed as a proof concept.},
	doi = {10.1109/TCAD.2011.2119150},
	author = {Samuel Rodrigo {Mocholi} and Flich, Jos{\'e} and Roca, Antoni and Medardoni, Simone and Bertozzi, Davide and Camacho, Jesus and Silla, Federico and Duato, Jose}
}
@inproceedings {Simula.simula.504,
	title = {IFDOR - Dynamic Rerouting On-Chip},
	journal = {Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip},
	year = {2011},
	month = {January},
	pages = {11-14},
	publisher = {ACM},
	type = {Workshop},
	address = {New York, USA},
	abstract = {Many-core chip design requires flexible routing solutions for the interconnect to handle faults, provide performance partitions, and react to dynamic changes in processing requirements and power/heat distribution. We have developed a logic based rerouting mechanism suitable for tolerating dynamic powering down of regions within the application partition on the chip. This mechanism is combined with the logic based FDOR routing algorithm to create a powerful routing algorithm with low implementation cost. This allows for higher system utilisation through enabling more efficient power management as well as supporting many irregular mesh topologies through flexible virtualisation. Results show that powering down a single switch results in an 8\% throughput reduction in the worst case for the evaluated topology.},
	isbn = {978-1-4503-0272-2},
	author = {Frank Olaf {Sem-Jacobsen} and Samuel Rodrigo {Mocholi} and Skeie, Tor},
	editor = {Flich, Jos{\'e} and Bertozzi, Davide}
}
@inproceedings {Simula.simula.510,
	title = {Addressing Manufacturing Challenges With Cost-Efficient Fault Tolerant Routing},
	journal = {NOCS {\textquoteright}10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip},
	year = {2010},
	pages = {25-32},
	publisher = {IEEE Computer Society},
	type = {Conference},
	isbn = {ISBN: 978-0-7695-4053-5},
	doi = {10.1109/NOCS.2010.12},
	author = {Samuel Rodrigo {Mocholi} and Flich, Jos{\'e} and Roca, Antoni and Medardoni, Simone and Bertozzi, Davide and Camacho, Jesus and Silla, Federico and Duato, Jose},
	editor = {IEEE Computer {Society}}
}
@article {Simula.simula.518,
	title = {Efficient Implementation of Distributed Routing Algorithms for NoCs},
	journal = {IET Computers \& Digital Techniques},
	volume = {3},
	number = {5},
	year = {2009},
	month = {September},
	pages = {460-475},
	doi = {10.1049/iet-cdt.2008.0092},
	author = {Samuel Rodrigo {Mocholi} and Medardoni, Simone and Flich, Jos{\'e} and Bertozzi, Davide and Duato, Jose}
}
@inproceedings {Simula.ND.367,
	title = {Flexible DOR Routing for Virtualization of Multicore Chips},
	journal = {International Symposium on System-on-Chip},
	year = {2009},
	month = {October},
	publisher = {IEEE},
	type = {Conference},
	abstract = {The expected increase in number of cores on a single chip leads to the necessity of high-performance on chip interconnects (NoC). Furthermore, in order to fully utilize the abundance of cores, the chip is expected to support a number of applications running on the chip simultaneously. It is therefore necessary to partition the chip to support numerous applications without any risk of interference between them. The success of this depends on the flexibility of the underlying routing algorithm. This paper presents a flexible routing algorithm based on dimension ordered routing, which supports a large variety of irregular (2-D and 3-D) mesh topologies. The algorithm provides high efficiency at very low additional complexity, as is confirmed by experimental results.},
	isbn = {978-1-4244-4465-6},
	author = {Skeie, Tor and Frank Olaf {Sem-Jacobsen} and Samuel Rodrigo {Mocholi} and Flich, Jos{\'e} and Bertozzi, Davide and Medardoni, Simone},
	editor = {Nurmi, Jari and Takala, Jarmo and Vainio, Olli}
}
@inproceedings {Simula.simula.516,
	title = {Yield-Oriented Evaluation Methodology of Network-on-Chip Routing Implementations},
	journal = {SOC{\textquoteright}09 Proceedings of the 11th international conference on System-on-chip},
	year = {2009},
	publisher = {IEEE},
	type = {Conference},
	isbn = {978-1-4244-4466-3},
	doi = {10.1109/SOCC.2009.5335667},
	author = {Samuel Rodrigo {Mocholi} and Hernandez, Carles and Flich, Jos{\'e} and Silla, Federico and Duato, Jose and Medardoni, Simone and Bertozzi, Davide and Mej{\'\i}a, Andres and Dai, Donglai},
	editor = {IEEE, }
}
