@inproceedings {Simula.ND.71,
	title = {On the Potential of NoC Virtualization for Multicore Chips},
	journal = {International Workshop on Multi-Core Computing Systems (MuCoCoS{\textquoteright}08)},
	year = {2008},
	month = {March},
	pages = {801-807},
	publisher = {IEEE},
	type = {Workshop},
	abstract = {As the end of Moores-law is on the horizon, power becomes a limiting factor to the continuous increases in performance gains for single-core processors. Processor engineers have shifted to the multicore paradigm and many-core processors are reality. Within the context of these multi-core, three key metrics point themselves out as being of major importance, performance, fault-tolerance (including yield), and power consumption. A solution that optimizes all three of these metric is challenging. As the number of cores increases the importance of the interconnection network-on-chip (NoC) grows as well, and chip designers should aim to optimize these three key metrics. In this paper we identify and discuss the main properties that a NoC must exhibit in order to enable such optimizations. In particular, we propose the use of virtualization techniques at the NoC level. The implementation of routing algorithms for NoC is a key design parameter in order to achieve an effective virtualization of the chip that should also support broadcast within the virtualized context. The intention behind this paper is for it to serve a position paper on the topic of virtualization for NoC and the challenges that should be met at the routing layer in order to maximize performance, fault-tolerance and power consumption.},
	author = {Flich, Jos{\'e} and Samuel Rodrigo {Mocholi} and Duato, Jose and S{\o}dring, Thomas and {\r A}shild Gr{\o}nstad {Solheim} and Skeie, Tor and Lysne, Olav},
	editor = {Pllana, Sabri}
}
