@inproceedings {28037,
	title = {iPUG: Accelerating Breadth-First Graph~Traversals Using Manycore Graphcore~IPUs},
	journal = {High Performance Computing. ISC High Performance 2021},
	volume = {LNCS, volume 12728},
	year = {2021},
	pages = {291-309},
	publisher = {Springer International Publishing},
	address = {Cham},
	abstract = {The Graphcore Intelligence Processing Unit (IPU) is a newly developed processor type whose architecture does not rely on the traditional caching hierarchies. Developed to meet the need for more and more data-centric applications, such as machine learning, IPUs combine a dedicated portion of SRAM with each of its numerous cores, resulting in high memory bandwidth at the price of capacity. The proximity of processor cores and memory makes the IPU a promising field of experimentation for graph algorithms since it is the unpredictable, irregular memory accesses that lead to performance losses in traditional processors with pre-caching.This paper aims to test the IPU{\textquoteright}s suitability for algorithms with hard-to-predict memory accesses by implementing a breadth-first search (BFS) that complies with the Graph500 specifications. Precisely because of its apparent simplicity, BFS is an established benchmark that is not only subroutine for a variety of more complex graph algorithms, but also allows comparability across a wide range of architectures.We benchmark our IPU code on a wide range of instances and compare its performance to state-of-the-art CPU and GPU codes. The results indicate that the IPU delivers speedups of up\&nbsp;to\&nbsp;4{\texttimes}4{\texttimes}\&nbsp;over the fastest competing result on an NVIDIA V100 GPU, with typical speedups of about\&nbsp;1.5{\texttimes}1.5{\texttimes}\&nbsp;on most test instances.},
	keywords = {BFS, Graph500, IPU, Performance optimization},
	isbn = {978-3-030-78712-7},
	issn = {0302-9743},
	doi = {10.1007/978-3-030-78713-4},
	url = {https://link.springer.com/10.1007/978-3-030-78713-4},
	author = {Burchard, Luk and Moe, Johannes and Daniel Thilo {Schroeder} and Pogorelov, Konstantin and Langguth, Johannes},
	editor = {Bradford L. {Chamberlain} and Varbanescu, Ana-Lucia and Ltaief, Hatem and Luszczek, Piotr}
}
@article {26461,
	title = {Performance optimization and modeling of fine-grained irregular communication in UPC},
	journal = {Scientific Programming},
	volume = {2019},
	year = {2019},
	month = {03/2019},
	pages = {Article ID 6825728},
	publisher = {Hindawi},
	abstract = {The UPC programming language offers parallelism via logically partitioned shared\&nbsp;memory, which typically spans physically disjoint memory sub-systems.\&nbsp;One convenient feature of UPC is\&nbsp;its ability to automatically execute between-thread data movement,\&nbsp;such that the entire content of a shared data array appears to be freely\&nbsp;accessible by all the threads. The\&nbsp;programmer friendliness, however, can come at the cost of substantial\&nbsp;performance penalties. This is especially true when indirectly indexing\&nbsp;the elements of a shared array, for which the induced between-thread data\&nbsp;communication can be irregular and have a fine-grained pattern.\&nbsp;In this paper we study performance enhancement strategies specifically targeting\&nbsp;such fine-grained irregular communication in UPC.\&nbsp;Starting from explicit thread privatization,\&nbsp;continuing with block-wise communication, and arriving at message condensing and\&nbsp;consolidation, we obtained considerable performance improvement of UPC\&nbsp;programs that originally require fine-grained irregular communication.\&nbsp;Besides the performance enhancement strategies, the main contribution of the present paper is to propose performance models for the different scenarios, in form of quantifiable formulas that hinge on the actual volumes of\&nbsp;various data movements\&nbsp;plus a small number of easily obtainable hardware characteristic parameters.\&nbsp;These performance models help to verify the enhancements obtained, while also providing insightful predictions of\&nbsp;similar parallel\&nbsp;implementations, not limited to UPC, that also involve between-thread or\&nbsp;between-process irregular communication. As a further validation,\&nbsp;we also apply our performance modeling methodology and hardware\&nbsp;characteristic parameters to an existing UPC code for solving a 2D\&nbsp;heat equation on a uniform mesh.},
	keywords = {Fine-grained irregular communication, performance modeling, Performance optimization, Sparse matrix-vector multiplication, UPC programming language},
	doi = {https://doi.org/10.1155/2019/6825728},
	url = {https://www.hindawi.com/journals/sp/2019/6825728/},
	author = {Lagravi{\`e}re, J{\'e}r{\'e}mie and Langguth, Johannes and Prugger, Martina and Einkemmer, Lukas and Phuong H. {Ha} and Cai, Xing}
}
