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2020
J. Camacho, T. Skeie and S. Reinemo. System and method of computing ethernet routing paths In US Patent. H04L45/02 ed., 2020.
2019
J. Camacho, T. Skeie and S. Reinemo. Method of computing balanced routing paths in fat-trees In Us Patent. H04L45/14 ed., 2019.PDF icon us10425324.pdf (4.92 MB)
2016
T. Skeie, E. Tasoulas, F. Zahid, E. G. Gran and J. Camacho. About Management of Exascale Systems In ExaComm 2016, Frankfurt., 2016.PDF icon exacomm_2016_talk.pdf (9.65 MB)
2011
S. R. Mocholi, J. Flich, A. Roca, S. Medardoni, D. Bertozzi, J. Camacho, F. Silla and J. Duato. "Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems." IEEE Transactions on Computed Aided Design 30 (2011): 534-547.
S. Rodrigo, J. Flich, S. Medardoni, D. Bertozzi, J. Camacho, F. Silla and J. Duato. "Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30 (2011): 534-547.
2010
S. R. Mocholi, J. Flich, A. Roca, S. Medardoni, D. Bertozzi, J. Camacho, F. Silla and J. Duato. Addressing Manufacturing Challenges With Cost-Efficient Fault Tolerant Routing In NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, Edited by I. C. Society. IEEE Computer Society, 2010.