| Authors | J. D. Trotter, J. Langguth and X. Cai |
| Title | Quantifying data traffic of sparse matrix-vector multiplication in a multi-level memory hierarchy |
| Afilliation | Scientific Computing |
| Project(s) | Meeting Exascale Computing with Source-to-Source Compilers |
| Status | Published |
| Publication Type | Poster |
| Year of Publication | 2018 |
| Date Published | 06/2018 |
| Place Published | London, UK |
| Abstract | Sparse matrix-vector multiplication (SpMV) is the central operation in an iterative linear solver. On a computer with a multi-level memory hierarchy, SpMV performance is limited by memory or cache bandwidth. Furthermore, for a given sparse matrix, the volume of data traffic depends on the location of the matrix non-zeros. By estimating the volume of data traffic with Aho, Denning and Ullman’s page replacement model [1], we can locate bottlenecks in the memory hierarchy and evaluate optimizations such as matrix reordering. The model is evaluated by comparing with measurements from hardware performance counters on Intel Sandy Bridge. |
| Citation Key | 26157 |
By thinking constantly about it…
